Suhas Shivapakash

State of art deep neural network (DNN) models are both memory prohibitive and computationally intensive with millions of connections. Employing these models for an embedded mobile application is resource limited with large amount of power consumption and significant bandwidth requirement (to access the data from the external DRAM). In a custom FPGA hardware the bandwidth access from the DRAM is two to three times higher, compared to the MAC (Multiply-Accumulate) operation. In this paper, we propose a power efficient multi-bit neural network accelerator, where we employ the technique of truncating the partial sum (PSum) results from the previous layer before feeding it into the next layer. We demonstrate that, using our multi-bit accelerator, accuracy is maintained upto bit width of 12. The proposed truncation scheme has 50% power reduction and resource utilization was reduced by 16% for LUTs (Look-up tables), 9% for FFs (Flip-Flops), 19% for BRAMs (Block RAMs) and 7% for Digital Signal Processors (DSPs) when compared with the 32 bits architecture. A large network, AlexNet was used as a benchmark DNN model and Kintex-7 KC705 FPGA was used to test the architecture. Find out more

Future planetary and deep space exploration require robust methods of operation to operate spacecraft in the outer atmosphere without any variations or faults. The best fault tolerant method which can be used for operations of this kind is the class of Genetic Algorithms (GA) which are a sort of evolutionary algorithm. In this domain of operation, a combinational circuit is designed by the method of Cartesian Genetic Programming (CGP). The Circuit after the design is fed to the two GAs, namely, HsClone and Roulette. The main advantage in this use of GA is the likely determination of the best possible circuit within the space of a thousand circuits. The combinational circuit design is applied to both the algorithms and tested for fitness. After the required fitness is obtained, both the algorithms are compared with respect to their cumulative generational fitness and other allied aspects. The better algorithm will hence be determined to integrate it into the future design of spacecraft hardware. This is expected to help the spacecraft recover from Single Event Upsets (SEU) which usually occur due to hostile temperature conditions and outer atmospheric radiation. Find out more

Deep space research and planetary exploration requires that the space vehicles should have robust system and reconfigurable architecture in the unpredictable environment. During this scenario there is a drastic need to develop a hardware architecture that can provide evolved hardware architecture in deep space environment, for this reason we will develop an evolutionary design of electronic circuits or an evolvable hardware that allows the On-Board Computer (OBC) to automatically obtain the desired circuit design configuration. This Evolvable Hardware technology that is developed will help to maintain the functionality of the design even in the presence of faults and degradation due to ageing, temperature and radiation. The key benefits are spacecraft survivability, to carry out new mission requirements, adaptation to new mission requirements and mission reliability. This Evolvable Hardware technology also helps in interplanetary mission taken by the space agency. The entire circuit configuration uses Evolutionary Algorithm, where one such algorithm is the Genetic Algorithm. Genetic Algorithm (GA) is the heuristic algorithm that operates on the population of solution and applies the principle of survival of fittest to provide better approximation to solution. In this research a combinational circuit is designed using Cartesian Genetic Programming (CGP) and is applied to three GA`s namely: HsClone, Roulette and Compact which is tested for fitness. After the required fitness is obtained, all the algorithms are compared for generational fitness and other allied aspects. Finally the better algorithm is found out so that it can operate on the spacecraft to recover from Single Event Upsets which occurs mainly due to unpredictable hostile environment conditions.

State of art deep neural network (DNN) models are both memory prohibitive and computationally intensive with millions of connections. Employing these models for an embedded mobile application is resource limited with large power consumption and significant bandwidth requirement. In this paper, we propose a power efficient multi-bit neural network accelerator, where we employ the technique of truncating the partial sum (PSum) results from the previous layer before feeding it into the next layer. Find out more

In this work, we present a 9-bit source-series-terminated digital-to-analog driver with a closely tied echo canceler. Designed and fabricated in 22nm FDSOI process, the transmitter achieves 5 Gb/s data rate with PAM4 under chip-on-board assembly. The measured differential eye-opening is 1V. The measured peak-to-peak data jitter is 110ps and has the power efficiency for the main DAC of 4.5 mW/Gb/s. The driver pair is suitable for Automotive Ethernet Standards 1GBase-T1, 2.5GBase-T1 and 5GBase-T1. The transmitter with the echo canceler dissipates 42mV and 3mV of power from a 1.2V I/O supply and 0.8V core supply,respectively. Find out more

Zigbee module was employed with EM35XX development kit.